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发明名称
降低次定限电流用之负性充电字元线
摘要
本发明提供一种降低记忆体磁芯单元中之次定限电流的方法。本发明提供具有复数之记忆体磁芯单元的记忆体阵列。每一记忆体阵列的记忆体磁芯单元可利用一字元线来选定。用以定址一特定记忆体磁芯单元的一被选定之字元线被充电至正电压。此外,不被选定之记忆体阵列的字元线被充电至负电压。依此方式,而降低与不被选定之记忆体磁芯单元连接的次定限电流。
申请公布号
TW200425158
申请公布日期
2004.11.16
申请号
TW093101009
申请日期
2004.01.15
申请人
亚提森元件公司
发明人
史考特T. 贝克
分类号
G11C7/00
主分类号
G11C7/00
代理机构
代理人
许峻荣
主权项
地址
美国
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