发明名称 REPLICA CIRCUIT WITHOUT A PHASE SPLITTER
摘要 PURPOSE: A replica circuit is provided to secure the reliability by installing the test load into the replica and adjusting the resistance of the test load resistor and the capacitance value in response to the usage of the test load. CONSTITUTION: A replica circuit includes a clock path model unit(210), a test load model unit(220) and a clock buffer model unit(230). The clock path model unit(210) performs the modeling of the components to perform the operations after the delay line except the clock buffering operation. The test load model unit(220) performs the modeling of the test load mounted after the output pad and processes the output signal of the clock path model unit(210). And, the clock buffer model unit(230) generates the inner clock signal by receiving the output signal of the test load model unit(220).
申请公布号 KR20040095977(A) 申请公布日期 2004.11.16
申请号 KR20030027011 申请日期 2003.04.29
申请人 HYNIX SEMICONDUCTOR INC. 发明人 PARK, HYEON HO
分类号 G11C11/407;(IPC1-7):G11C11/407 主分类号 G11C11/407
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