Performing secure address relocation within a multi-processor system sharing a same physical memory channel to external memory

摘要

In response to receiving a selection to override an existing memory allocation of one or more regions of an external memory device within a memory register for a particular bridge from among multiple bridges within an integrated circuit, wherein the multiple bridges connect to a shared physical memory channel to the external memory device, a remap controller of the particular bridge reads, from a super rank register, one or more super rank values specifying one or more relocation regions of the external memory device connected to an interface of the integrated circuit. The remap controller remaps the memory register for the particular bridge with the one or more super rank values specified in the super rank register to relocate memory accesses by the bridge to the one or more relocation regions of the external memory device.

主权项

1. A system for performing secure address relocation, comprising:
an integrated circuit comprising a plurality of bridges connected through a shared physical memory channel to one or more external memory devices connected to one or more interfaces of the integrated circuit; the integrated circuit operative, in response to receiving a selection to override an existing memory allocation of one or more regions of the one or more external memory devices within a memory register for a particular bridge from among the plurality of bridges, to trigger a remap controller of the particular bridge, to read from a super rank register, one or more super rank values specifying one or more relocation regions of the one or more external memory devices; and the remap controller operative to remap the memory register for the particular bridge with the one or more super rank values specified in the super rank register to relocate memory accesses by the bridge to the one or more relocation regions of the one or more external memory devices, wherein one or more processor units are connected to each of the plurality of bridges within a single integrated circuit device, wherein only a particular processor unit of the integrated device is allowed to set the super rank register values.