| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit and its inspection method for avoiding a problem, without changing the expectation value pattern, that a semiconductor integrated circuit is erroneously determined to be defective due to the disagreement between the data obtained from the output terminal of the integrated circuit and the value pattern because of a phenomenon called as cycle lag in which an output signal of an asynchronous circuit is delayed by a time length equating to an integral multiple of a clock signal period with respect to an actual operation test on the integrated circuit equipped with the asynchronous circuit. SOLUTION: A delay output circuit 11 is provided for delaying, before its outputting, the output signal 4 of the asynchronous circuit by a time length obtained by multiplying the period of a second clock signal 3 by "a value m expressed by a prescribed fixed value N-cycle delay period number setting signal 12". Even if a cycle lag arises in the output signal 4 of the asynchronous circuit, the output signal 4 of the asynchronous circuit is outputted to the output terminal 5 at the same time by using the same value as the period number of the cycle lag as the value m of the setting signal 12, making it possible to perform correct inspection by using the same expectation value pattern. COPYRIGHT: (C)2005,JPO&NCIPI
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