| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a delay locked loop to which an external clock signal is directly inputted. <P>SOLUTION: A delay locked loop provided with a level selection part, a control signal generating part, and an internal clock signal generating part. The level selection part receives the external clock signal and outputs it as it is in response to a control signal, or changes the level of the external clock signal and outputs it as a converted external clock signal. The control signal generating part generates a control signal. The internal clock signal generating part receives an output of the level selection part and an external clock signal and generates an internal clock signal locked with the output phase of the level selection part. The level selection part is provided with a selection control part and a clock buffer part amplifies the level of the level control signal up to the CMOS level. The external clock signal has a TTL level. The level selection part receives the external clock signal through a specified repeater circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
