| 摘要 |
PROBLEM TO BE SOLVED: To solve a problem that since the driving voltage of an avalanche photodiode (APD) is as high as 100-300V, reliable isolation is required for fabricating a single chip CMOS FET and the element structure is complicated significantly. SOLUTION: In the APD 10, a P<SP>-</SP>region (P well) 12 having a concentration (1E15-1E17 cm<SP>-3</SP>) substantially equivalent to that of the P well in CMOS process is formed on an N type substrate 11, a P type diffusion layer, i.e. an avalanche region (P layer) 15, and a high concentration N<SP>+</SP>diffusion layer, i.e. a surface high concentration layer 14, are formed in the P well 12, and a high concentration P<SP>+</SP>layer 16 is formed at a surface position isolated from the surface high concentration layer 14 by an isolation film 13. The APD 10 has a structure compatible with the CMOS process well, operates on a low voltage of 50V or below and can be integrated with a CMOSFET easily. COPYRIGHT: (C)2005,JPO&NCIPI
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