| 摘要 |
A system and method for simulating clock drift between asynchronous clock domains. In one embodiment, a first circuit portion is positioned in a first clock domain to transmit a first data sequence. An intermediate circuit portion receives the first data sequence and, responsive to a control signal, transmits a second data sequence to a second circuit portion positioned in a second clock domain. The second data sequence is subjected to drift relative to the first data sequence.
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