| 摘要 |
Disclosed is a programmable buffer circuit (16) for interfacing a CPU (12) to a plurality of channel interfaces (14). The buffer circuit includes a dual port memory (18) having a first port coupled to a CPU data bus and a second port coupled to a channel data bus that serves the plurality of channel interfaces. The buffer circuit further includes an arbitrator (24) for arbitrating access to the dual port memory by individual ones of the channel interfaces over the channel data bus; an address generator (26) for generating dual port memory addresses for reading and writing data using the CPU data bus and the channel data bus; and a control unit (20) and allocator (22) that are programmable by the CPU for specifying individual ones of buffer locations and sizes within the dual port memory for individual ones of the channel interfaces, and for enabling and disabling individual ones of the buffers. The allocator has outputs coupled to the address generator for controlling the generation of addresses thereby, depending on which channel interface is currently selected for access to the dual port memory. The control unit is programmable for operating individual ones of the channel buffers in a block access mode or in a first in/first out (FIFO) access mode of operation. In a preferred embodiment, at least the dual port memory, the CPU and the plurality of interface channels are contained within a common integrated circuit package, such as an ASIC. By example, one of the plurality of interface channels implements an audio CODEC, another one implements a serial data interface, and another one implements a packet data interface channel. Individual ones of the plurality of interface channels contain a receive interface and a transmit interface, and the allocator includes a corresponding plurality of registers for specifying at least a starting address and a size for each of of the receive interface and the transmit interface. The buffer circuit is also programmable for specifying a receive buffer of one channel interface to be a transmit buffer of another channel interface.
|
