发明名称 Apparatus for evaluating lithography process margin simulating layout pattern of semiconductor device
摘要 A layout pattern generating unit within a lithography process margin evaluating apparatus generates a plurality of design layout patterns, using an analysis condition and information stored in a layout pattern template holding unit. In addition, a simulation condition generating unit generates a plurality of simulation conditions, using the analysis condition and information stored in a simulation condition template holding unit. A simulation unit generates a plurality of actual layout patterns, using a generated condition. Thus, the lithography process margin evaluating apparatus can reduce operational burden and improve accuracy.
申请公布号 US2004225993(A1) 申请公布日期 2004.11.11
申请号 US20040870934 申请日期 2004.06.21
申请人 发明人
分类号 G03F1/08;G03F1/14;G03F1/36;G03F1/68;G03F1/70;G03F7/20;H01L21/027;(IPC1-7):G06F17/50;G06F19/00 主分类号 G03F1/08
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