| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To speed up a reading speed of electrically rewritable on-chip nonvolatile memory. <P>SOLUTION: The nonvolatile memory has a hierarchized bit line structure comprising a first bit line (BL) unique to each of two or more memory arrays (21), a second bit line (GBLr) common to the two or more memory arrays, a first selection circuit which selects the first bit line for each memory array and is able to connect it to the second bit line, and a sense amplifier (SA) arranged between the output of the first selection circuit (22) and the second bit line. The hierarchized bit line structure by the division of the memory arrays reduces the input load capacity of the sense amplifier. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
