| 摘要 |
PROBLEM TO BE SOLVED: To improve development efficiency by enabling early detection of a design error even when there is an error in circuit design or layout design. SOLUTION: A cell arrangement section 15 arranges a cell having the respective circuit sign and a layout corresponding area and displays it on a screen based on a circuit design file storage section 12 and a cell storage section 11. A wiring section 16 connects the respective arranged cells with each other by wire with a separate layout corresponding width and displays it on the screen based on a circuit design file. A signal analysis section 17 simulates inputting of an electric signal into a specified place of semiconductor integrated circuits displayed on the screen, analyzes signal levels among the respective cells including wiring delay based on the layout corresponding width and wiring length of the wiring, and displays the acquired signal level on the wiring with different colors for the respective levels. Thereby, the circuit design, the layout design and the result of signal analysis are displayed simultaneously, and the above mentioned problem is solved. COPYRIGHT: (C)2005,JPO&NCIPI
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