发明名称 PEAK-HOLD CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a circuit that realizes faster rise in an output potential without changing components, even though there is a limit in speed up because the time constant of potential rising on the output side of a conventional peak hold circuit is determined by a product of three items: a resistance value connected to the output side while a diode is conductive, a capacitor capacitance, and the reciprocal of the mark rate of signal. <P>SOLUTION: In the peak-hold circuit, an input amplifier having a differential output is provided. Elements, having first and second rectification characteristics are connected to the output sides of both positive phase and negative phase of the input amplifier. The output side of the elements, having first and second rectification characteristics, are connected to one electrode of the same capacitor, while the other electrode of the capacitor is connected to a reference potential. An electric charge discharging means is provided, to discharge the electric potential which is accumulated in the capacitor. In this way, the time constant circuit of a fullwave rectification type substantially makes the time constant decrease to half with the conventional components left as they are. <P>COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2004317456(A) 申请公布日期 2004.11.11
申请号 JP20030115266 申请日期 2003.04.21
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 NOGAWA MASASHI;KAWAMURA TOMOAKI
分类号 G01R19/165;G01R19/04;G11C27/00;H03K5/1532 主分类号 G01R19/165
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