| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock signal detection circuit capable of detecting whether a clock signal is supplied or not with high accuracy while reducing a circuit scale and suppressing power consumption. SOLUTION: This clock signal detection circuit has: a tristate buffer circuit 2 generating an output signal of prescribed electric potential when the clock signal is in a first level, and making an output terminal in a high impedance state when the clock signal is in a second level; a resistor 5 connected between the output terminal of the tristate buffer circuit 2 and electric potential different from the prescribed electric potential; and a buffer circuit 3 generating a clock signal detection result according to the output electric potential of the tristate buffer circuit 2. COPYRIGHT: (C)2005,JPO&NCIPI
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