| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory apparatus which can attain area saving, acceleration and power reduction. SOLUTION: The memory device is provided with bit lines (BL1 to BL3), word lines (WL1 to WL3) arranged so as to intersect the bit lines (BL1 to BL3), and a memory cell 1 which is connected to the bit lines (BL1 to BL3) and the word lines (WL1 to WL3) and includes a storing means having hysterisis. The center of a hysterisis loop of the memory cell 1 including the storing means is deviated from 0V for a prescribed potential (k(V)) so as to make the type of voltage to be applied to the bit lines (BL1 to BL3) and the word lines (WL1 to WL3) to be three types. COPYRIGHT: (C)2005,JPO&NCIPI
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