发明名称 TWO POLES ANALOG MONITOR VOLTAGE GENERATING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide two poles analog monitor voltage generating circuit in which positive/negative voltages can be outputted from an output of ASIC with a single power source. SOLUTION: In a digital/analog converter, a D-flip flop 2 holds data when BRM1 outputs it to Y, and an output signal P<SB>1</SB>of the D-flip flop 2 becomes a pulse of one clock time (one period width). In the output signal P<SB>1</SB>, a NAND gate and an inverter superimpose data on an original clock CK, an output P<SB>3</SB>is obtained from BRM, and a synthesized pulse is integrated so as to obtain analog voltage. The clock CK of BRM1 is inverted in the inverter 5, and a capacitor 7 performs AC coupling. Diodes 8 and 9 perform clamping and rectification. Thus, voltage obtained by inverting power voltage, and voltage and the output P<SB>3</SB>from BRM1 are synthesized at an integral point. Consequently, the two poles analog monitor voltage generating circuit is realized. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2004320515(A) 申请公布日期 2004.11.11
申请号 JP20030112608 申请日期 2003.04.17
申请人 YASKAWA ELECTRIC CORP 发明人 HARA KENJI
分类号 H03M1/82;H03K21/10;H03K23/64;(IPC1-7):H03M1/82 主分类号 H03M1/82
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