发明名称 |
Chip scale package and method of fabricating the same |
摘要 |
Disclosed are a chip scale package and a method of fabricating the chip scale package. The chip scale package comprises an insulating layer formed on the upper surface of a chip provided with a plurality of terminals on its one surface, a plurality of conductive layers formed on the insulating layer and spaced from each other by a designated distance so as to be connected to each of a plurality of the terminals, and a plurality of electrode surfaces formed on each of the upper surfaces of a plurality of the conductive layers. The chip scale package is miniaturized in the whole package size. Further, the method of fabricating the chip scale package does not require a wire-bonding step or a via hole forming step, thereby simplifying the fabrication process of the chip scale package and improving the reliability of the chip scale package.
|
申请公布号 |
US6815257(B2) |
申请公布日期 |
2004.11.09 |
申请号 |
US20020329519 |
申请日期 |
2002.12.27 |
申请人 |
SAMSUNG ELECTRO-MECHANICS CO., LTD. |
发明人 |
YOON JOON HO;CHOI YONG CHIL;BAE SUK SU |
分类号 |
H01L23/12;H01L21/301;H01L21/304;H01L21/60;H01L23/04;H01L23/31;H01L23/485;H01L33/38;H01L33/62;H05K3/34;(IPC1-7):H01L21/44 |
主分类号 |
H01L23/12 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|