发明名称 Semiconductor memory device including ferroelectric memory formed using ferroelectric capacitor
摘要 A semiconductor memory device includes a memory cell block, gate lines and branch lines. The memory cell block includes memory cells connected in series. Each of memory cells has a cell transistor having a source and a drain and a ferroelectric capacitor inbetween the source and the drain. The gate lines are connected to the gates of the cell transistors of the memory cell block. The gate lines have a predetermined width and are arranged at regular intervals. The branch lines are formed of a layer different from that of the gate lines, arranged parallel to the gate lines, and each connected thereto. The branch lines have a predetermined width and are arranged at regular intervals. The sum of the width of the branch lines and the interval between adjacent branch lines differing from the sum of the width of the gate lines and the interval between adjacent gate lines.
申请公布号 US6816399(B2) 申请公布日期 2004.11.09
申请号 US20030400565 申请日期 2003.03.28
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 HOYA KATSUHIKO;TAKASHIMA DAISABURO
分类号 G11C11/22;H01L21/768;H01L21/8246;H01L23/522;H01L27/105;H01L27/115;(IPC1-7):G11C11/22 主分类号 G11C11/22
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