TRI-LAYER MASKING ARCHITECTURE FOR PATTERNING DUAL DAMASCENE INTERCONNECTS,申请号WO2003US09700-传众专利搜索

发明名称	TRI-LAYER MASKING ARCHITECTURE FOR PATTERNING DUAL DAMASCENE INTERCONNECTS
摘要	<p>This invention relates to a method of dual damascene integration for copper based wiring in a low-k dielectric stack (120, 130, 140) using three top hard mask layers (150, 160, 170) having alternating etch selectivity characteristics, and being, for example, inorganic/organic/inorganic.</p>
申请公布号	WO03085724(A8)	申请公布日期	2004.11.04
申请号	WO2003US09700	申请日期	2003.03.28
申请人	DOW GLOBAL TECHNOLOGIES INC.;TOWNSEND, PAUL, H., III;MILLS, LYNNE, K.;WAETERLOOS, JOOST, J., M.;STRITTMATTER, RICHARD, J.	发明人	TOWNSEND, PAUL, H., III;MILLS, LYNNE, K.;WAETERLOOS, JOOST, J., M.;STRITTMATTER, RICHARD, J.
分类号	H01L21/3065;H01L21/027;H01L21/033;H01L21/311;H01L21/312;H01L21/316;H01L21/768;(IPC1-7):H01L21/768	主分类号	H01L21/3065
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