发明名称 FREQUENCY/PHASE-LOCKED LOOP CLOCK SYNTHESIZER USING FULL DIGITAL FREQUENCY DETECTOR AND ANALOG PHASE DETECTOR
摘要 <P>PROBLEM TO BE SOLVED: To provide a frequency/phase-locked loop clock synthesizer using a full digital frequency detector and an analog phase detector. <P>SOLUTION: A frequency synthesizer suited to integration in a low-voltage digital CMOS process controls a VCO using a double loop structure including an analog loop and a digital loop. In the digital loop, there is the full digital frequency detector that controls a central frequency of the VCO. In the analog loop, there is the analog phase detector with a charge pump which adds phase coherence to a frequency control loop so that a static frequency error does not occur. Actually, the analog loop reduces noise of a digital logic and the VCO, and digital control supplies frequency hold-over and extremely low bandwidth. The bandwidth of the digital loop is made extremely smaller than that of the analog loop. <P>COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2004312726(A) 申请公布日期 2004.11.04
申请号 JP20040099210 申请日期 2004.03.30
申请人 SEIKO EPSON CORP 发明人 MELTZER DAVID;BLUM GREGORY
分类号 H03L7/187;H03D13/00;H03L7/087;H03L7/113 主分类号 H03L7/187
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