| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of being appropriately evaluated. SOLUTION: Line addresses are sequentially shifted to be allocated by a memory cell array MSA10 at a shift processing circuit 5. According to twisted parts and shifting, at a data inversion determination part 8, bit line pairs BL1 to B128 in which word lines WL21 to WL512 designated b the input line addresses and wiring position replacement parts CCAR10 and CCAR11 intersect each other are discriminated to determine the inversion of the level of an evaluation testing data D8 input/output from the bit line pairs BL1 to BL128. By inverting the level of the evaluation testing data D8 input/output from the bit line pairs BL1 to BL128 at an inversion processing part 4, the evaluation testing data D8 of "0" and "1" levels are accurately stored for each cell by a storage pattern. The data is output by canceling the inversion of the storage time during reproducing, and the semiconductor memory device can appropriately be evaluated. COPYRIGHT: (C)2005,JPO&NCIPI
|
