| 摘要 |
PROBLEM TO BE SOLVED: To obtain a semiconductor device that can be reduced in on-resistance without increasing turning-off loss and, in addition, can be increased in withstand voltage. SOLUTION: In a PT type IGBT having a planer structure, an n-type buffer layer 2 having a width of 40μm and a peak concentration of 1×10<SP>16</SP>cm<SP>-3</SP>on a p<SP>-</SP>-type layer 3a side is formed on the rear surface of an n-type base layer 1 having an impurity concentration of 1×10<SP>13</SP>cm<SP>-3</SP>and a p-type emitter layer 3 composed of the p<SP>-</SP>-type layer 3a having a thickness of 5μm and the peak concentration of 1×10<SP>16</SP>cm<SP>-3</SP>and a p<SP>+</SP>-type layer 3b having a thickness of 1μm and a peak concentration of 7×10<SP>17</SP>cm<SP>-3</SP>is formed on the rear surface of the buffer layer 2. In addition, a collector electrode 12 is formed on the p<SP>+</SP>-type layer 3b. COPYRIGHT: (C)2005,JPO&NCIPI
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