发明名称 Encoded video data synthesis apparatus
摘要 <p>An encoded video data synthesis apparatus includes: a decoding unit having N, that is, two or more, decoders for decoding input encoded video data; an encoding unit having N encoders for encoding image data from the decoding unit; a buffer unit having N buffers which can store the encoded video data as a process result of the encoding unit for a predetermined number of frames; a stream synthesis unit for performing a synthesizing process on the encoded video data of one frame from each buffer; and a control unit for issuing an instruction to perform a synthesizing process to the stream synthesis unit. The encoded video data synthesis apparatus can further include a frame memory unit having N frame memory which can store a predetermined number of pieces of image data from a decoding unit between a decoding unit and an encoding unit.</p>
申请公布号 GB0421886(D0) 申请公布日期 2004.11.03
申请号 GB20040021886 申请日期 2004.10.01
申请人 FUJITSU LIMITED 发明人
分类号 H04N19/423;H04J3/00;H04N5/91;H04N7/15;H04N7/24;H04N19/00 主分类号 H04N19/423
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