| 摘要 |
PURPOSE: A DLL circuit is provided to operate normally even when a period of an external input clock is short. CONSTITUTION: A clock buffer(10) receives an external clock signal, and a delay circuit(20) receives an output signal of the clock buffer. A clock divider(50-1) divides an output signal of the clock buffer, and a dummy delay circuit(60) delays an output signal of the clock divider. A replica delay unit(90) delays an output signal of the dummy delay circuit. A phase comparator compares a phase of an output signal of the replica delay unit with a phase of the output signal of the clock divider. A delay controller(80) controls delay of the delay circuit and the dummy delay circuit by receiving an output signal of the phase comparator. A clock signal line(30) controls data output of an output buffer(40) by receiving an output signal of the delay circuit. And a clock pulse width detector(100) detects pulse width of the clock signal by receiving the output signal of the clock buffer.
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