CLOCK DIVIDER OF DLL DEVICE AND ITS CLOCK DIVIDING METHOD, ESPECIALLY REDUCING CURRENT CONSUMPTION

摘要

PURPOSE: A clock divider of a DLL device and its clock dividing method are provided to reduce current consumption by reducing the number of phase comparison in a DLL circuit when a memory device is in a power down mode. CONSTITUTION: The first divider(400) outputs a clock signal(A) having a half frequency of an input signal(S1) by dividing the input signal. The second divider(410) outputs a clock signal(B) having a half frequency of an input clock signal(A) by dividing the input clock signal. The third divider(420) outputs a clock signal(C) having a half frequency of an input clock signal(B) by dividing the input clock signal. The fourth divider(430) outputs a clock signal(D) having a half frequency of an input clock signal(C) by dividing the input clock signal. And a power down controller(500) receives output clock signals of the third and the fourth divider and selects one of the output clock signals according to a logic level of a clock enable signal(CKE).