发明名称 System transmitting data in equidistance cycles using successive synchronization signals for detecting and signaling access violations
摘要 A user terminal (1) having a communications processor (10) that carries out a cyclic data transmission. During a cyclic part (ZYK,x) of a cycle (Z,x) in which user data are transmitted, a DP application may not access the memory (14, 15). In the communications processor (10), the memory (14, 15) stores a process image. The communications processor (10), for the purpose of synchronization, transmits at the beginning of a cycle a cycle start interrupt (ZSI,x) and at the end of the cyclic part (ZYK,x) a cycle end interrupt (ZEI,x). Once the arithmetic unit (5, 7, 8) has accessed the memory it releases the interrupts. The duration (DeltaT's2,1; DeltaT'e2,1) between two successive interrupts serves to detect access violations and to initiate appropriate fault treatment measures.
申请公布号 US6813664(B2) 申请公布日期 2004.11.02
申请号 US20030355109 申请日期 2003.01.31
申请人 SIEMENS AKTIENGESELLSCHAFT 发明人 KOELLNER CHRISTOPH;KATZENBERGER OTMAR;MENSINGER JOERG;RUDI HEINRICH
分类号 G05B19/042;G05B19/418;H04L12/403;(IPC1-7):G06F13/36 主分类号 G05B19/042
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