| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device capable of realizing an SOI integrated circuit of a complete depleting operation and low parasitic resistance, minimizing the damage of the SOI layer surface of a channel formation part while provided with a recess structure, minimizing a crystal defect while suppressing stress even at the end part of a channel region and suppressing the generation of a leakage current due to it, and provide its manufacturing method. SOLUTION: In a semiconductor memory composed of a gate electrode 14 formed through a gate insulation film 15 on an SOI substrate having an SOI layer 3 on the surface, the channel region right below the gate electrode 14 and source / drain regions formed on both sides of the channel region, the film thickness of the SOI layer 3 is different at a channel region center part, a channel end part and the source / drain regions and the gate electrode 14 is formed wider on a channel region side than at the middle part. COPYRIGHT: (C)2005,JPO&NCIPI
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