发明名称 INTEGRATED CIRCUIT HAVING REORGANIZABLE FUNCTION OF LOGICAL FUNCTION AND ITS DESIGN METHOD
摘要 PROBLEM TO BE SOLVED: To provide a method for efficiently realizing a symmetrical function among logical functions and an arbitrary k-input variable logical function by using a neuron MOS circuit and the neuron MOS circuit having functions of the logical functions. SOLUTION: Each input vector is distinguishable by determining weight to each of k-pieces of input variables with a designated method. When using organizing data of a function of a binary logical function, a preinverter corresponding in one-to-one to each input vector is fixed, and logical values of output signals of the corresponding preinverter and logical values of second input signals as the data organizing the function of the logical function are made to correspond to each other. An arbitrary function of the logical function is realized by performing one-to-one correspondence between the logical values of the output signals of the preinverter and the logical values of the output signals of the preinverter. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2004303262(A) 申请公布日期 2004.10.28
申请号 JP20040141722 申请日期 2004.05.11
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 AOYAMA KAZUO;SAWADA HIROSHI;NAGOYA AKIRA
分类号 G06N3/063;H01L21/82;(IPC1-7):G06N3/063 主分类号 G06N3/063
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