发明名称 SCANNING METHOD 3 WEIGHT-ADDED RANDOM SCAN BUILT-IN SELF-TEST CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a scanning method 3 weight-added random scan built-in self-test circuit for reducing test sequence length and hardware overhead in 3 weight WRPT BIST (test-per-clock and scanning method). SOLUTION: This scanning method built-in self-test circuit is to produce a test set for sensing any failure hard to be detected. It identifies a set of failures hard to detect, and then uses an advanced automatic test pattern generator to produce the test set for sensing any failure hard to be detected. In this case, it applies the advanced automatic test pattern generator so as to allow for both hardware overhead and test sequence length, while making the hardware overhead to be generated when a new test cube is added to the test set. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2004301856(A) 申请公布日期 2004.10.28
申请号 JP20040183137 申请日期 2004.06.21
申请人 NEC CORP 发明人 SONMUN WAN
分类号 G01R31/28;G01R31/3181;G01R31/3183;G01R31/3185;G06F11/22;G06F11/263;G06F11/27;(IPC1-7):G01R31/28;G01R31/318 主分类号 G01R31/28
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