Method and logical apparatus for rename register reallocation in a simultaneous multi-threaded (SMT) processor

摘要

A method and logical apparatus for rename register reallocation in a simultaneous multi-threaded (SMT) processor provides a mechanism for redistributing rename (mapped) resources between one thread during single-threaded (ST) execution and multiple threads during multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. The internal control logic then signals the resources to reallocate the resources. Rename resources are reallocated by directing an action at the rename mapper. Specifically, on a switch from SMT to ST mode, the mapper is directed to drop entries for the dying thread, but on a switch from ST to SMT mode, "dummy" instruction group dispatch indications are sent to the mapper that indicate use of all registers, so that mapper entries are deleted from the pool of entries used by the previously-executing "surviving" thread to make room for rename entries needed by another "reviving" thread that is being started for further execution in SMT mode.