发明名称 |
INTEGRATED CONTENT ADDRESSABLE MEMORY ARCHITECTURE |
摘要 |
A novel ten-transistor (10-T) content addressable memory (CAM) cell and an integrated CAM architecture. A six-transistor (6-T) static random access memory (SRAM) cell and a four-transistor (4-T) comparator module of the 10-T CAM cell are respectively coupled to different bit lines for preventing any disturbance at a match line associated with the 10-T CAM. Each row of the integrated CAM architecture includes a valid bit cell combined with a protect bit cell and at least a mask cell with global resetting function to sufficiently ensure the correction and flexibility during comparing operations.
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申请公布号 |
US2004213027(A1) |
申请公布日期 |
2004.10.28 |
申请号 |
US20030249588 |
申请日期 |
2003.04.22 |
申请人 |
LIU KWO-JEN;WANG HSIN-SHIH |
发明人 |
LIU KWO-JEN;WANG HSIN-SHIH |
分类号 |
G11C15/04;(IPC1-7):G11C15/00 |
主分类号 |
G11C15/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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