METHOD AND APPARATUS FOR TESTING ASYNCHRONOUS SET/RESET FAULTS IN A SCAN-BASED INTEGRATED CIRCUIT

摘要

A method and apparatus to test data set/reset faults in a scan-based integrated circuit in a selected scan-test mode. or self-test mode. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The method comprises shifting in a plurality of predetermined stimuli during scan-test, or pseudo-random stimuli during self-test to the scan-based integrated circuit, using a set/reset enable (SR-EN 383) and a scan enable (SE 382) signal to capture faults to each scan cell, and shifting out the test responses for comparison or compaction. The apparatus or set/reset controller (375) further comprises using the set/reset enable (SR-EN 383) and scan enable (SE 382) signals to selectively propagate data faults or set/reset faults to the scan cells in the integrated circuit. Computer-aided design methods are proposed to automatically repair all asynchronous set/reset signals in the integrated circuit, and generate test patterns for verifying the correctness of the repaired integrated circuit.