| 摘要 |
The present invention relates to an electronic device utilizing code compression, which device comprises a pipeline processor (25), a branching unit (26) which allows the address of the next instruction to be anticipated, a code decompression unit (27), and a memory (28), a new set of compressed instructions being defined for the combined processor (25), branching unit (26) and decompression unit (27). The decompression unit (27) is suitable for sending two signals for the start and end of a loop to the branching unit (26) by decoding the start-of-loop and end-of-loop labels which have been introduced into the new set of instructions. The branching unit (26) processes these two signals. The present invention also relates to a management method for a processor of this kind. |
