发明名称 |
SIMULATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT |
摘要 |
PROBLEM TO BE SOLVED: To provide a method for carrying out simulation in an actual element configuration by creating a netlist reflecting a layout pattern of elements. SOLUTION: In a semiconductor integrated circuit to be designed, S101 carries out simulation to the elements in the semiconductor integrated circuit created by a semiconductor integrated circuit creation means by; specifying precision for every element at the time of simulation at S102; generating a netlist of the above circuit diagram at S103; reading a library of the above element at S104; and using the above netlist and the above library at S105. COPYRIGHT: (C)2005,JPO&NCIPI
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申请公布号 |
JP2004302499(A) |
申请公布日期 |
2004.10.28 |
申请号 |
JP20030091197 |
申请日期 |
2003.03.28 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
KUMASHIRO SHINICHI |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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地址 |
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