发明名称 |
MPEG ARTIFACTS POST-PROCESSED FILTERING ARCHITECTURE |
摘要 |
<p>A more efficient and less memory-access intensive post-processing architecture to substantially reduce blocking and ringing artifacts from decompressed video image data is provided. The post-processing architecture in accordance with the present invention implements a "pipelined" filtering process wherein a filter buffer, a blocking filter, and a ringing filter are serially connected to each other. The serial connection allows decompressed video image data to be first provided to a blocking filter for substantially reducing blocking artifacts and then the de-blocked video image data can be provided directly to a ringing filter for de-ringing without the need of an extra memory access.</p> |
申请公布号 |
WO2004093330(A2) |
申请公布日期 |
2004.10.28 |
申请号 |
WO2004US11288 |
申请日期 |
2004.04.12 |
申请人 |
NVIDIA CORPORATION;ZHONG, LEFAN;BABBAGE II, DAVID NOEL |
发明人 |
ZHONG, LEFAN;BABBAGE II, DAVID NOEL |
分类号 |
G06T5/00;H04B;H04N7/12;H04N7/26;H04N11/02;H04N11/04;(IPC1-7):H04B/ |
主分类号 |
G06T5/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|