摘要 |
<p>A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of instructions from the instruction word in parallel. A detection unit, detects in which of a plurality of ranges the instruction address lies. The detection unit is coupled to the instruction execution unit and/or the instruction memory system, to control a way in which the instruction execution unit parallelizes processing of the instructions from the instruction word, dependent on a detected range. In an embodiment the instruction execution unit and/or the instruction memory system adjusts a width of the instruction word that determines a number of instructions from the instruction word that is processed in parallel, dependent on the detected range.</p> |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V.;SETHURAMAN, RAMANATHAN;SRINIVASAN, BALAKRISHNAN;ALBA PINTO, CARLOS, A.;PETERS, HARM, J., A., M.;PESET LLOPIS, RAFAEL |
发明人 |
SETHURAMAN, RAMANATHAN;SRINIVASAN, BALAKRISHNAN;ALBA PINTO, CARLOS, A.;PETERS, HARM, J., A., M.;PESET LLOPIS, RAFAEL |