发明名称 |
Method of manufacturing MOS transistor having short channel |
摘要 |
The MOS transistor of the present invention is manufactured by a conventional complementary MOS transistor technology. In the manufacturing method of the MOS transistor having nanometer dimensions, a gate having dimensions at a nanometer scale can be formed through control of the width of spacers instead of with a specific lithography technology. The doped spacers are used for forming source/drain extension regions having an ultra-shallow junction, thereby avoiding damage on the substrate caused by ion implantation. In addition, a dopant is diffused from the doped space into a semiconductor substrate through annealing to form the source/drain extension regions having an ultra-shallow junction.
|
申请公布号 |
US2004214382(A1) |
申请公布日期 |
2004.10.28 |
申请号 |
US20040834306 |
申请日期 |
2004.04.27 |
申请人 |
PARK IL-YONG;KIM SANG-GI;YU BYOUNG-GON;KIM JONG-DAE;ROH TAE-MOON;LEE DAE-WOO;YANG YIL-SUK |
发明人 |
PARK IL-YONG;KIM SANG-GI;YU BYOUNG-GON;KIM JONG-DAE;ROH TAE-MOON;LEE DAE-WOO;YANG YIL-SUK |
分类号 |
H01L21/225;H01L21/336;H01L29/78;(IPC1-7):H01L21/336;H01L21/823;H01L21/476 |
主分类号 |
H01L21/225 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|