| 摘要 |
A Viterbi decoder with a reduced number of bits in branch metric calculation processing is disclosed. In a branch metric calculator, word split circuits divide metric data 1 to 3 from respective latch circuits into the signs of the least 1 bit and metrics of k-1 bits, respectively. EX-OR gates determine whether or not the divided signs (1 bit) match codewords (1 bit) for each state produced from a convolutional code generated by a convolutional code generator and a counter. Each time-division switch for 1 bit selects the output of the match or mismatch with switched timing. Adders add outputs when the signs match to the divided metrics output from selectors when the signs do not match based on the selection to calculate a branch metric.
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