发明名称 RAM functional test facilitation circuit with reduced scale
摘要 The outputs of selectors 230 to 23N are respectively connected to the data inputs DI0 to DIN of a RAM 10A. One inputs of selectors 540 to 54N are respectively connected to the data outputs DO0 to DON of the RAM 10A, the other inputs are connected to corresponding outputs of the selectors 230 to 23N. The outputs of the selectors 540 to 54N are connected to data inputs D of respective scan flip-flops 520 to 52N. Not in a RAM test mode, data input lines 210 to 21N are selected by the selectors 230 to 23N to provide to the data inputs DI0 to DIN of the RAM 10A and to the scan flip-flops 520 to 52N through the selectors 540 to 54N, respectively.
申请公布号 US6810498(B2) 申请公布日期 2004.10.26
申请号 US20020106052 申请日期 2002.03.27
申请人 FUJITSU LIMITED 发明人 SHIMIZU RYUJI
分类号 G01R31/28;G06F11/22;G06F12/16;G11C29/12;(IPC1-7):G01R3/28 主分类号 G01R31/28
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