发明名称 |
Semiconductor integrated circuit compensating variations of delay time |
摘要 |
A semiconductor device includes a first circuit and a second circuit cascaded therefrom, a pattern examination section for examining the input signal pattern for the first circuit to estimate a delay in the first circuit, a delay control block for controlling an internal source potential based on the estimated delay for controlling the source potential for the second circuit so that the signal delay from the second circuit has small variations of delay time. The integrated circuit can be formed on a reasonable specification, and achieves a lower dissipation and a higher reliability.
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申请公布号 |
US6810497(B2) |
申请公布日期 |
2004.10.26 |
申请号 |
US20010767945 |
申请日期 |
2001.01.24 |
申请人 |
NEC ELECTRONICS CORPORATION |
发明人 |
YAMADA TAKASHI |
分类号 |
G11C11/413;G06F1/10;G11C7/10;G11C7/22;G11C11/407;H01L21/822;H01L27/04;H03K5/00;H03K5/13;H03K19/0175;(IPC1-7):G11R31/28;H03H11/26 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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