| 摘要 |
A multi-channel circuit (1) comprising three channels (CH1 to CH3), each of which is provided with a current steering DAC (5) in which crosstalk between the respective DACs (5) is minimized. Each DAC (5) comprises binary scaled current source devices (Qs1 to Qsn) and current steering switches (Qt1 and Qf1 to Qtn to Qfn) for steering currents from the current source devices (Qs1 to Qsn) to summing nodes (11,12) across which an analogue signal is developed corresponding to a digital input word. Cascode devices (Qc1 to Qcn) are provided between the respective current source devices Qs1 to Qsn and the corresponding current steering switches (Qt1 and Qf1 to Qtn and Qfn) for preventing capacitive feedthrough of voltage swings on the current steering switches (Qt1 and Qf1 to Qtn and Qfn) for minimizing crosstalk between the DACs (5). Gates of the cascode devices (Qc1 to Qcn) of DACs (5) are biased from corresponding cascode bias voltage circuits (25), and the gates of the cascode devices (Qc1 to Qcn) of each DAC (5) are isolated from the gates of the cascode devices (Qc1 to Qcn) of the other DACs (5) also for minimizing crosstalk.
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