发明名称 |
Method for fabricating 6F2 trench DRAM cell with double-gated vertical MOSFET and self-aligned STI |
摘要 |
A memory cell containing double-gated vertical metal oxide semiconductor field effect transistors (MOSFETs) and isolation regions such as shallow trench isolation, STI, regions that are self-aligned to the wordlines and bitlines of the cell are provided. The inventive memory cell substantially eliminates the backgating problem and floating well effects that are typically present in prior art memory cells. A method of fabricating the inventive memory cell is also provided.
|
申请公布号 |
US6808981(B2) |
申请公布日期 |
2004.10.26 |
申请号 |
US20030375654 |
申请日期 |
2003.02.27 |
申请人 |
IBM |
发明人 |
MANDELMAN JACK A;DIVAKARUNI RAMACHANDRA;RADENS CARL J;BRONNER GARY B |
分类号 |
H01L21/8234;H01L21/8242;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/8234 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|