METHOD FOR FABRICATING HIGH VOLTAGE DEVICE TO REDUCE ON-RESISTANCE OF TRANSISTOR

摘要

PURPOSE: A method for fabricating a high voltage device is provided to reduce on-resistance of a transistor and improve an operation speed by reducing a dose quantity in a threshold voltage ion implantation process and by decreasing an interval of an annealing process for channel diffusion. CONSTITUTION: A channel ion implantation process is performed at a dose quantity of 3.7x10¬13. An annealing process is performed for an interval of 80 minutes on the resultant structure having undergone the channel ion implantation process. The annealing process is performed at a temperature of 1080 deg.C.