SYNCHRONOUS DRAM CAPABLE OF REDUCING AUTO REFRESH TIME, ESPECIALLY INCLUDING ROW DECODERS AND ADDRESS BUFFERS AND BANK ADDRESS BUFFERS AND REFRESH ROW COUNTER

摘要

PURPOSE: A synchronous DRAM capable of reducing auto refresh time is provided, which accesses to other banks while performing auto refresh and reduces the auto refresh time. CONSTITUTION: According to the synchronous DRAM, a plurality of banks(201,203) are controlled independently. A plurality of row decoders(205,207) select rows of a memory cell array of each bank. A plurality of row address buffers(211) store row addresses. A plurality of bank address buffers(209) store bank addresses. A control signal generator(213) generates internal control signals in response to external control signals. A refresh row counter(215) is controlled by the control signal generator and generates a refresh row address. And a selector unit(217) selects one of outputs of the refresh row counter and the row address buffer, and then transfers it to the plurality of row decoders. The output of the bank address buffer is transferred to the row decoder directly without passing through the selector unit. And the refresh row counter is constituted with the same number of bits as the row address buffer.