An overlay metrology mark for determining the relative position between two or more layers of an integrated circuit structure comprising a first mark portion associated with and in particular developed on a first layer and a second mark portion associated with and in particular developed on the surface of a second layer, wherein each mark portion comprises a single two dimensional generally orthogonal array of individual test structures. A method of marking and a method of determining overlay error are also described.
申请公布号
WO2004090978(A2)
申请公布日期
2004.10.21
申请号
WO2004GB01533
申请日期
2004.04.08
申请人
AOTI OPERATING COMPANY, INC.;SMITH, NIGEL, PETER;HAMMOND, MICHAEL, JOHN