发明名称 ARITHMETIC UNIT AND MULTIPLYING UNIT
摘要 PROBLEM TO BE SOLVED: To provide an arithmetic unit which multiplies a decimal digit by suppressing the increase of a circuit area and to provide a multiplying unit. SOLUTION: The value of a binary number having 4 bits is input as a signal Ain [3:0] and a signal Bin [3:0] to a binary number multiplier 21. The binary number multiplier 21 multiplies the input two values, and outputs its product as a signal Xout [7:0]. A six times compensator 22 multiplies a signal Xout [7:4] by six times, and outputs a signal Cin [7:0]. A BCD converter 23 adds (6)d when the 4 less significant bits of the signal Xout [7:0] is 10 or more, and outputs a signal Din [7:0]. A decimal number adder 24 adds the signal Cin [7:0] to the signal Din [7:0], and outputs the sum as a signal BcdFaOut [7:0]. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2004295345(A) 申请公布日期 2004.10.21
申请号 JP20030085148 申请日期 2003.03.26
申请人 CASIO COMPUT CO LTD 发明人 NAKAE TETSUKAZU
分类号 G06F7/496;G06F7/52;G06F9/305;(IPC1-7):G06F7/52 主分类号 G06F7/496
代理机构 代理人
主权项
地址