发明名称 PLL circuit and television receiver having same and beat reducing method for television receiver
摘要 A PLL circuit is used for a super-heterodyne television receiver. In the PLL circuit, a reference signal oscillator circuit generates a reference signal, and the reference signal is compared to a LO signal in a phase comparator. The phase comparator includes (i) an oscillating circuit, (ii) a series circuit of a correcting capacitor and an oscillator corresponding to a predetermined IF signal frequency, (iii) another correcting capacitor, and (iv) a switch. The switch is turned ON or OFF only when receiving a particular channel in which interference occurs, so as to shift the frequency of the reference signal by several ten kHz. This reduces beats in a particular channel, and prevents deterioration of picture quality in other channels. That is, interference in a particular channel can be reduced without causing any adverse effects in other channels having a relatively high frequency.
申请公布号 US2004207476(A1) 申请公布日期 2004.10.21
申请号 US20040781672 申请日期 2004.02.20
申请人 ITAYA TSUYOSHI 发明人 ITAYA TSUYOSHI
分类号 H03J3/20;H03J5/24;H03L7/18;H04B1/10;H04B1/26;H04N5/12;H04N5/21;H04N5/44;H04N5/50;(IPC1-7):H03K3/26 主分类号 H03J3/20
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