发明名称 Timing information generating apparatus
摘要 A timing information generating apparatus includes an input/output information identifying unit, a delay time calculating unit and a timing information output unit. The input/output information identifying unit compares logical connection information with a library to identify intra-block input stage sequential circuits contributing to information exchange with extra-block input stage sequential circuits, and intra-block output stage sequential circuits contributing to information exchange with extra-block output stage sequential circuits. According to timing constraint information, the delay time calculating unit sets first delay times from input pins to the intra-block input stage sequential circuits, and second delay times from the intra-block output stage sequential circuits to output pins. The timing information output unit outputs timing information including the first delay times and the second delay times.
申请公布号 US2004210689(A1) 申请公布日期 2004.10.21
申请号 US20030689592 申请日期 2003.10.22
申请人 RENESAS TECHNOLOGY CORP. 发明人 TANAKA GENICHI
分类号 G06F17/50;G06F1/10;(IPC1-7):G06F3/00 主分类号 G06F17/50
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