发明名称 Input circuit with hysteresis
摘要 An input circuit has hysteresis to mitigate the effects of input noise. The input circuit receives an analog input signal and determines whether the unregulated analog input signal is a high or a low voltage. The input circuit outputs a regulated low voltage (i.e., "0") for a low input signal, and outputs a regulated high voltage (i.e., "1") for a high input signal. The low-to-high transition occurs at a higher voltage than a high-to-low transition, which mitigates noise on the input signal. Furthermore, the comparator includes a feedback path from an output of the comparator to an input of the comparator. The feedback path causes some delay in any output voltage transition (i.e. high-to-low output transition or low-to-high transition), which further enhances the hysteresis effect and improves noise immunity. An embodiment of the circuit interfaces with high voltage (e.g., 5V) input signals and outputs low voltage (e.g., 1.2V) output signals. In other words, the input circuit also provides a voltage transition while detecting the low-to-high and high-to-low transitions.
申请公布号 US2004207438(A1) 申请公布日期 2004.10.21
申请号 US20040845352 申请日期 2004.05.14
申请人 AJIT JANARDHANAN S. 发明人 AJIT JANARDHANAN S.
分类号 H03K3/013;H03K3/356;H03K3/3565;(IPC1-7):H03K3/037 主分类号 H03K3/013
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