发明名称 |
Valid bit generation and tracking in a pipelined processor |
摘要 |
In an embodiment, a pipelined digital signal processor (DSP) may generate a valid bit in an alignment stage. The valid bit may be qualified in a decode stage in response to receiving a stall signal and/or a kill signal. The valid bit output from the decode stage may be stored in a latch in an address calculation (AC) stage. The valid bit may be held in the latch by a latch enable circuit in response to receiving a stall signal. The valid bit output from the latch may be qualified in the AC stage. The circuit in the AC stage including the latch, the latch enable circuit, and a valid bit qualifier may be repeated in downstream pipeline stages, for example, the execution stages.
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申请公布号 |
US2004210744(A1) |
申请公布日期 |
2004.10.21 |
申请号 |
US20040847837 |
申请日期 |
2004.05.17 |
申请人 |
INTEL CORPORATION, A DELAWARE CORPORATION;ANALOG DEVICES, INC., A DELAWARE CORPORATION |
发明人 |
ROTH CHARLES P.;SINGH RAVI P.;OVERKAMP GREGORY A.;TOMAZIN THOMAS |
分类号 |
G06F9/38;(IPC1-7):G06F9/30 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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