发明名称 Column select circuit of ferroelectric memory
摘要 A column select gate in a ferroelectric memory is constituted by only P-channel MOS transistors. While a column select signal is set to low level, and a data line is set to 0 V, data is read out from a memory cell to a bit line. A potential amplified and held by a sense amplifier is transferred to the data line through the current path of the column select gate formed from the P-channel MOS transistors.
申请公布号 US2004208045(A1) 申请公布日期 2004.10.21
申请号 US20030671468 申请日期 2003.09.29
申请人 SHIRATAKE SHINICHIRO 发明人 SHIRATAKE SHINICHIRO
分类号 G11C7/10;G11C11/22;(IPC1-7):G11C11/22 主分类号 G11C7/10
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